| 8:45-9:15 |
Refreshments, Registration & Expo |
|
| 9:15-9:20 |
Welcome |
by Shuka Zernovizky, SemIsrael
|
| 9:20-9:45 |
UVM apps: cool UVM gadgets to upgrade your testbench |
by Avidan Efody, Verification Specialist, Mentor Graphics
|
| 9:45-10:10 |
New Levels of Verification IP Productivity for SOC Verification |
by Yaron Ilani, Senior Application Consultant, Synopsys |
| 10:10-10:35 |
Deploying Formal Property Verification |
by Avner Landver, Ph.D. CEO, Karmel Electronic Design Services |
| 10:35-11:00 |
Coverage for formal verification.
Is it really needed? |
by Ziyad Hanna PhD, Jasper VP of Research and Chief Architect, Jasper Isreal GM |
| 11:00-11:25 |
Algorithmic Modules Verification Suite |
Asi Lifshitz, Verification team leader, Veriest Venture |
| 11:25-11:50 |
Coffee, Snacks & Visit to the Expo |
|
| 11:50-12:15 |
FPGA based Prototype and how to debug it |
by Uri Golan, Senior Applications Consultant, Springsoft |
| 12:15-12:40 |
Checking on Accelerators |
by Ronny Morad, Manager, System Verification Technologies, IBM Research - Haifa |
| 12:40-13:05 |
“See-Thru” your Prototype; Cigol’s FPGA Verification Vision |
by Avi Rabinovich, Product Manager, Cigol Digital Systems |
| 13:05-13:30 |
Advanced methodologies for system performance validation |
by Yoav Arnon, VP Technical Services, Satris Group |
| 13:30-15:00 |
Lunch,Lucky Draw, Visit to the Expo |
|
