Brite Semiconductor Improves Quality of Results and Reduces Time to Market for Four SoC Designs with Cadence Digital Implementation and Signoff Tools

HANGHAI, China and SAN JOSE, Calif., March 2, 2015—Cadence Design Systems, Inc. (NASDAQ: CDNS), today announced that Brite Semiconductor Corporation, used Cadence® digital implementation and signoff tools to complete four 28nm system-on-chip (SoC) designs and reduced their time to market by three weeks compared to previous design methodologies. By using Cadence tools, Brite Semiconductor was also able to increase performance by up to 20 percent and reduce power consumption by up to 10 percent on these designs.

Brite Semiconductor adopted the Cadence Encounter® Digital Implementation System for physical implementation and Voltus™ IC Power Integrity Solution for power signoff and design closure. The Encounter Digital Implementation System, which incorporates GigaOpt route-driven optimization along with CCOpt concurrent clock datapath optimization, helped Brite Semiconductor to improve performance and reduce power consumption. In addition, the Voltus IC Power Integrity Solution enabled Brite Semiconductor to validate, very early on, that the designs function as intended, which minimized the risk of design failures later in the process and ultimately reduced development time.

"In the highly competitive mobile market, it's important that we have the right digital implementation and signoff tools to help us stay ahead of the competition," said Thomas Xu, Chief Operating Officer of Brite Semiconductor. "The efficiencies of the Cadence Encounter Digital Implementation System and the Voltus IC Power Integrity Solution have helped us to achieve our goals. Not only have we optimized performance and power, we've also been able to shorten time to market (TTM) by up to 10 percent and enhance the reliability of our designs."

"The Cadence tools enabled Brite Semiconductor to improve quality of results and engineering productivity which helps them deliver their 28nm SoC designs designs on time," said Dr. Anirudh Devgan, senior vice president of the Design & Signoff Group at Cadence. "Saving three weeks in the design schedule means that Brite Semiconductor can take on more new, innovative design projects because they have the ability to get more designs to market faster."