Veriest Solutions to present at CDNLive! conference in Munich

Veriest Solutions, a leading VLSI Design & Verification services company, will be presenting at Cadence’s CDNLive! Conference in Munich on 15-17 of May.

The topic of Veriest presentation will be “How to Get the Most out of HLS-High Level Synthesis”, which is the state-of-the-art technique in Digital Design.

With HLS, one can easily generate abstract C-language models and synthesize optimized hardware from those models, than can be later retargeted to different technology platforms and reused more easily than traditional hand-coded RTL. Therefore, it is possible to actively make tradeoffs between power, area, and performance from within the HLS environment. Veriest has accumulated experience in HLS-based design across different technologies and projects.

The Veriest team will be also available to meet customer in booth #21.

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