Real Intent to Exhibit at DVCon Europe 2018 Next Week


Real Intent will showcase its new Verix family of products, including the recently announced PhyCDC product for gate-level CDC sign-off and SimFix for eliminating X-pessimism, as well as its Ascent and Meridian products for RTL sign-off, at DVCon Europe 2018 in Munich, Germany October 24-25, 2018.

Exhibit Information:

Booth 203

Holiday Inn Munich City Centre

10:00am-7:00pm, Wednesday October 24th

10:00am-6:30, Thursday October 25th

For more information on DVCon Europe 2018, visit here.

Products on display include:

  • Verix PhyCDC is the company’s new tool for debugging clock domain crossing violations at the gate level netlist of digital designs. It targets the post-synthesis stage of SoC design at the gate level, and leverages the results from RTL CDC to identify incremental CDC paths and constraints to optimize the CDC analysis while providing maximum coverage. For more information on Verix PhyCDC, a whitepaper and data sheet are available.

  • Verix SimFix automatically eliminates X-pessimism, the major obstacle to successful GLS and boosts productivity for SoC design teams. This new product also extends Real Intent's product leadership in delivering the industry's fastest performance, highest capacity, and most productive verification solutions in the market. For more information on Verix SimFix, a whitepaper and data sheet is available.

  • Verix CDC is a true multi-mode clock-domain crossing (CDC) sign-off solution for RTL designs. Utilizing Static Intent Verification technology, it provides one-step analysis and debug of all operating modes in an IC, and boosts productivity for SoC and FPGA design teams. It also maintains Real Intent's product leadership in delivering what the company believes is the industry's fastest-performance, highest-capacity and most precise CDC solution in the market. For more on Verix CDC, a whitepaper and data sheet are available.

  • The Meridian products are for advanced static clock and reset sign-off verification not possible with existing tools.

Real Intent’s Hierarchical capability, introduced for Meridian CDC, has now been extended to Meridian RDC. It delivers cutting edge sign-off for billion-gate SoCs using the industry’s first Transparent Hierarchical Model (THM). The THM-based signoff flow provides an order of magnitude improvement in performance, capacity with giga-gate sign-off, and noise when applied to large SoC designs.

  • Meridian CDC performs comprehensive structural and functional analysis to ensure that signals crossing asynchronous clock domains on ASIC, or FPGA devices are received reliably. Meridian CDC is the only solution that enables all aspects of big data CDC sign-off for SoC designs.

  • Meridian RDC (Reset Domain Crossing) performs comprehensive static analysis to ensure that signals crossing reset domains function reliably. Among other things, Meridian RDC identifies metastability problems arising from software resets. Meridian RDC is the only solution with giga-gate capacity that enables comprehensive lowest-noise reset domain crossing sign-off.

  • Ascent Lint is the industry’s fastest RTL linter and rule checker for full-chip SoC analysis. Designed from the bottom-up to deliver the highest performance, capacity and low-noise reporting, it is the best-in-class HDL linter available today with a comprehensive set of syntax and semantic checks.

  • iDebug provides an intuitive debug user experience that is universal across all Real Intent tools. It includes an integrated visualization capability, iVision, that provides design source browser, schematic and waveform visualization. It also includes a new Intent Wizard platform that provides unprecedented gains in static sign-off productivity. The Intent Wizard platform uses comprehensive data generated by Real Intent’s static sign-off application engine and combines that with the Root Cause Analysis technology within iDebug to cut the debug time in half.