Aldec Increases Verification Productivity with the latest release of Riviera-PRO

Henderson, NV – July 12, 2016 – Aldec, Inc., today announced the latest release of its Advanced Verification Platform, Riviera-PRO™ 2016.06. Riviera-PRO is a tightly integrated solution for functional verification of complex System-on-Chip (SoC), ASIC and FPGA designs. The new release of Riviera-PRO offers enhanced support for Metric-Driven Verification, significant performance improvements in Constrained Random Verification (CRV), as well as new debugging features designed to increase verification productivity.
“Metric-Driven Verification has become a significant methodology for increasing the overall verification coverage,” said Radek Nawrot, Riviera-PRO Product Manager. “It requires the right tools and features to enable a simple and transparent way to carry out the complicated process of verification. Riviera-PRO 2016.06 new features include Finite State Machine (FSM) Coverage, Design Units Viewer, Datasets Window and Covergroup Viewer.”
Riviera-PRO 2016.06 offers up to 20% speed up in simulation of designs using XilinxCoreLib simulation libraries, SystemC testbench and SystemVerilog constrained random stimulus enabling users to run more regressions, therefore, improving the overall quality of verification.
Along with introducing the official support for 4K resolution monitors, Riviera-PRO 2016.06 also introduces a new debugging tool, The Contributors, which allows users to easily list the signals that have an influence on the tested part of a design.

The 2016.06 release of Riviera-PRO also includes numerous new features, enhancements, and performance optimizations. For additional information, tutorials, free evaluation download and What’s New Presentation, visit