AMIQ EDA Rearchitects Design Elaboration Engine for Faster Performance and Greater Accuracy

July 16, 2020, San Jose, California - AMIQ EDA, a pioneer in integrated development environments (IDEs) for hardware design and verification and a provider of platform-independent software tools for efficient code development and analysis, today announced that it has overhauled the design elaboration engine in its flagship Design and Verification Tools (DVT) Eclipse IDE to handle much larger and more complex system-on-chip (SoC) projects. The redesigned engine supports new IDE features requested by the most advanced hardware design teams.

Unlike traditional text editors or simple syntax checkers, DVT Eclipse IDE compiles and elaborates the complete design and builds an internal model. This enables easy navigation and precise, sophisticated checks with auto-correct and quick-fix options. While AMIQ EDA makes incremental enhancements in each new release, it has now rearchitected and redesigned the elaboration engine for a true next-generation solution with improved capacity and accuracy.

More designers are adopting DVT Eclipse IDE for designs growing ever larger and more complex, and they will see direct benefits from the enhanced elaboration process. Advanced editing capabilities, such as renaming ports across the design hierarchy and adding new ports or new parameters, are highly valuable for designers. They also benefit from easy tracing of signals and automatic generation of different diagrams and visualizations for the design and its hierarchy,

DVT Eclipse IDE supports SystemVerilog and VHDL, the two primary register-transfer-level (RTL) languages, and provides seamless navigation of mixed-language designs. It accurately elaborates incomplete designs from the early stages of a chip development project, allowing users to browse and manipulate the RTL code. The checks accurately identify incomplete or incorrect code, offering a wide range of auto-corrections and quick-fix suggestions to improve designer efficiency.

“The new engine is transparent to users, since no changes are needed to use it, but its benefits are visible.” said Cristian Amitroaie, CEO of AMIQ EDA. “Users now see precise design checks, greater capacity, and enhanced performance as the result of this major upgrade. DVT Eclipse IDE is well positioned to handle continued design expansion and accommodate ongoing customer requests for additional checks and other features.”

In addition to the RTL, DVT Eclipse IDE compiles and elaborates the complete design and verification environment, including testbench, assertions, and power intent files. It supports a wide range of languages and formats, including SystemVerilog, Verilog, VHDL, the e language, C/C++, Unified Power Format (UPF), the Universal Verification Methodology (UVM), and the Portable Stimulus Standard (PSS).

Availability and Pricing

The new features are available today in DVT Eclipse IDE. Pricing is available upon request. Live discussions and more information will be available at the Design Automation Conference (DAC), held online July 20-22 at AMIQ EDA will showcase all its products: DVT Debugger, Verissimo SystemVerilog Testbench Linter, and Specador Documentation Generator in addition to DVT Eclipse IDE.