AMIQ EDA Joins OpenHW Group and Contributes Linting Capabilities for CORE-V Open-Source RISC-V Cores and Testbenches

SAN JOSE, CALIFORNIA, UNITED STATES, November 23, 2021 - AMIQ EDA, a pioneer in integrated development environments (IDEs) for hardware design and verification and a provider of platform-independent software tools for efficient code development and analysis, today announced that the company has joined OpenHW Group, a provider of open-source RISC-V processor cores and related IP, tools, and software. AMIQ technology is being used by OpenHW Group in a continuous integration flow to analyze (“lint”) CORE-V SystemVerilog testbench code to automatically detect and suggest fixes for a wide range of issues.

“Simulators and other electronic design automation (EDA) tools detect some types of coding errors, but the OpenHW team was looking for a dedicated linting tool with more capabilities,” said Cristian Amitroaie, CEO of AMIQ EDA. “Our solution detects many types of issues, checking more than 700 rules for SystemVerilog and the Universal Verification Methodology (UVM), and offers suggestions for resolving them. Developers and users of OpenHW Group testbenches can be certain that their code is correct and follows industry best practices.”

The solution combines AMIQ EDA Design and Verification Tools (DVT) Eclipse Integrated Development Environment (IDE) and Verissimo SystemVerilog Linter, which can run in batch mode or within the IDE. Users can take full advantage of the IDE’s interactive environment to debug reported issues. Features include a smart source code editor, schematics, and diagrams for finite state machines (FSMs), design hierarchies, and class hierarchies.

“The OpenHW Verification Task Group was impressed that, from the very first runs, the AMIQ EDA solution identified important issues,” reported Rick O’Connor, President and CEO of OpenHW Group. “Some of these were violations of our existing SystemVerilog coding guidelines that we previously had no automated way to detect, and some were due to rules we had not considered before. We have confirmed and fixed dozens of these issues, so we have already seen the value of the enhanced linting, and analysis provided by AMIQ EDA.”

As part of the contribution to OpenHW Group, the AMIQ EDA team has established a pre-packaged open-source setup environment that makes it easy for users to continue to run linting on CORE-V testbench components as they integrate them into their system-on-chip (SoC) environments. The environment also allows users to examine and debug the Verissimo results within DVT Eclipse IDE. This setup is now in the OpenHW code repository and available to everyone. The RISC-V architecture has numerous options for user extensions and customizations, so users can also verify the integrity of any SystemVerilog code that they modify or add during the integration process.

AMIQ EDA has also established a continuous integration regression environment that runs lint analysis every six hours to pick up all recent changes to the cores or testbenches in the OpenHW Group repository. Reports are available at www.dvteclipse.com/core5verif-verissimo/1/main/index.html. While individual CORE-V developers are encouraged to take advantage of the pre-packaged environment to verify all code before it is contributed to the repository, proactive regressions ensure that all changes and additions to the code base are verified. AMIQ EDA has been running similar automated regressions for several years on the code in the UVM repository and this has proven highly beneficial. Reports are available at www.dvteclipse.com/uvm-verissimo/1/main/index.html