Mixel Announces Availability of the World’s First MIPI C-PHY/D-PHY Combo IP Supporting 30 Gbps

SAN JOSE, Calif. - Mixel®, a leading provider of mixed-signal intellectual property (IP), announced today that its MIPI® C-PHYSM/D-PHYSM IP compliant with the MIPI C-PHY v2.0 and MIPI D-PHY v2.5 specifications is now available. MIPI D-PHY supports MIPI Camera Serial Interface 2 (CSI-2SM) and Display Serial Interface (DSISM) and DSI-2SM. Mixel is the first IP provider to make this IP available to its customers, with the total aggregate speed reaching over 30 Gbps.

Mixel’s MIPI C-PHY/D-PHY combo IP is a high-frequency, low-power, low-cost, physical layer. It can be configured as a MIPI transmitter or receiver, supporting both the camera interface CSI-2 v3.0 and display interface DSI-2 v1.1 and is backward compatible with previous generations of each specification.

Mixel’s MIPI C-PHY v2.0 supports a speed of 4.5 Gsps per trio, an equivalent data rate of 10.26 Gbps/trio. In D-PHY mode, the IP supports speeds up to 4.5 Gbps per lane and complies with the MIPI D-PHY v2.5 specification. With up to three trios in C-PHY and up to four lanes in D-PHY, the combo IP reaches an aggregate bandwidth of 30.78 Gbps and 18Gbps in their respective modes.

The Mixel MIPI C-PHY/D-PHY Combo IP includes many new features to both the D-PHY and C-PHY that was not available in previous versions of the specifications, namely Spread Spectrum Clocking (SSC), transmit equalization (de-emphasis), and receiver ISI calibration. It also supports new power saving functionality such as HS-TX reduced swing modes and the HS-RX unterminated mode. The new Alternate LP Mode, suitable for IoT applications with long channels, is also supported, enabling Fast Bus Turnaround that boosts transmission bandwidth in the reverse direction of the MIPI link. The ALP Mode is central to the CSI-2 Unified Serial Link feature that reduces number of interface wires and helps to natively support longer reach. The combo PHY IP not only shares the serial interface pins, but Mixel's implementation also reuses all the MIPI D-PHY functional blocks for the MIPI C-PHY, minimizing area and leakage power.

“As a longtime contributing member and early IP provider for MIPI D-PHY and MIPI C-PHY, Mixel has been a valued advocate for the advancement and adoption of MIPI PHYs for many years,” said Joel Huloux, MIPI Alliance chairman. “With its latest announcement, Mixel advances the capabilities of SoC designers with its flexible, higher bandwidth combo solution.”

Mixel was the first IP provider to demonstrate silicon for MIPI D-PHY and MIPI C-PHY. Since then, Mixel’s MIPI PHY IP has been silicon-proven in 9 different nodes at 8 different foundries in multiple configurations including the patented RX+ configuration that allows for full-speed, in-system production testing with minimal overhead.

“We are thrilled to provide our customers with another industry first,” said Ashraf Takla, President and CEO of Mixel. “We continue to demonstrate Mixel’s commitment to our customers by developing leading edge MIPI IP to meet our customers’ demand for higher bandwidth in advanced technologies.”

Mixel will be showcasing its customers’ products at the MIPI Alliance’s annual Developers Conference, MIPI DevCon, to be held as a virtual event on September 22-23. Mixel will be also demonstrating its joint solution with Renesas at MIPI DevCon in a joint presentation titled “High-Speed MIPI CSI-2 Interface Meeting Automotive ASIL-B.”


Mixel MIPI C-PHY/D-PHY Combo IP is available now.

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For more information on Mixel’s IP portfolio, please visit https://mixel.com/ip-cores.