SmartDV’s LPDDR5 IP Clocks 612 MHz in FPGA Functional Test, 1.6GHz at 28nm

SAN JOSE, Calif., May 06, 2020 -- SmartDV™ Technologies today confirmed its LPDDR5 SDRAM controller design intellectual property (IP) achieved a speed of over 600 megahertz (MHz) in a field programmable gate array (FPGA) functional test and 1.6 gigahertz (GHz) in a 28-nanometer design during a recent competitive evaluation.

The highly configurable LPDDR5 IP scored higher than competitive offerings by delivering faster performance (e.g. clock rate), outperforming the closest competitor by 3X. It demonstrated a smaller footprint due to lower gate count and lower power, as well as lower latency.

“The recent completion of a technical qualification at a large semiconductor company calibrated the performance of our LPDDR5 controller IP and confirmed its exceptional competitive advantage," says Deepak Kumar Tala, SmartDV’s managing director. “We’re especially proud of the IP’s high performance that reached 612Mhz. The closest competitor came in at 200Mhz.”

SmartDV’s design IP targets multiple applications such as high-performance computing, networking, wearables, IoT and mobile, and can be rapidly customized to meet specific user needs. In addition to earlier versions of its LPDDR SDRAM controller IP, it supports the JESD209-5 LPDDR5 protocol standard specification. The IP is compatible with DFI 5.0 and supports a variety of host bust interfaces, including AHB, APB, OCP, TileLink, Wishbone, VCI and Avalon PLB. An open, flexible architecture ensures it can be used for any custom bus interface.

Availability and Pricing
The SmartDV LPDDR5 controller IP is delivered as soft design IP with register transfer level (RTL) source code and a comprehensive test suite that can be implemented in ASIC, system-on-chip (SoC) or FPGA designs.

Pricing is available upon request.

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