Tom Hsieh

Tom Hsieh

Sr. Manager, Applications Engineering, Custom Design and Physical Verification Group

Escalating chip complexity and scale is an ever-present theme in any integrated circuit (IC) design discussion. The challenges are becoming especially acute as we move to the era of hyper-convergent ICs, which are not only larger and more complex, but also introduce new requirements to perform multi-dimensional verification of these highly integrated system-level chips.

Simply throwing more horsepower at the problem is no longer sufficient (although still needed). A more productivity-oriented workflow is essential to deal with the variety of verification challenges in a modern system-on-chip (SoC). Multiple verification methods need to work in concert, and overall productivity is just as important as individual tool performance. It calls for a revamped verification strategy. Call it a continuum. This post, originally published in the “From Silicon to Software” blog, shares what you need to know.