SemIsrael Blogs

Please take a break to read SemIsrael blogs.

In January, Mentor will become Siemens EDA and this is exciting news for our EDA customers. Siemens enables us to bring high levels of investment in research and development, to build new products, and to acquire best-in-class electronic design companies. Mentor has always pioneered digitalization of electronic design and Siemens brings world-class digitalization to big systems like planes, automobiles, factories, and cities. Connecting electronic design to big systems is the vision for our customers.

I’m not alone in viewing each and every early-stage startup as a beacon of opportunity. Some of the most innovative and world-changing ideas I’ve seen in recent years have come from those only just starting out on their journey.

However, the challenges early-stage startups face are no secret: they need to build investor confidence to secure funding, they need to innovate quickly and they need to do so while minimizing costs along the way.

For Arm it’s incredibly important that we help fledgling companies with the potential to do something great to get off the ground. So today, we’re launching a new zero-dollar program, Arm Flexible Access for Startups, to give early stage startups access to a broad range of our world-leading technologies, spanning processor designs, tools and support.

Meeting tapeout schedules and performance requirements are equally critical conditions for IC design success. Now engineers can do both, using innovative P2P resistance checking to find and debug ESD errors in their layouts.

מדינות שונות שפות שונות ובפרט בסין דיאלקטים שונים. למרות זאת יש מדינות בהן המהנדסים כותבים אנגלית אולם ברובן ההנדסה כתובה בשפה המקומית. אף על פי כן השפה השיווקית בחלקת מהמדינות היא אנגלית. ביפן, סין וטייוון מפרטים טכניים יכתבו ביפנית/מנדרין אולם בקוריאה הדרומית והודו באנגלית.

Before we get started here, I’ll assure you it’s not as it sounds. I’m not talking about the end of coverage as though it’s something we’ll stop using. The end in this case is the home stretch of any non-trivial ASIC or FPGA development effort – which is almost all of them nowadays – where coverage collection, analysis and reporting consumes a team on its way to RTL signoff.

There is probably not one embedded system that is not built without open source software, 3rd party silicon IP or manufactured far from the design and distribution centers that make and sell these systems. Those who want to secure the design and delivery chain have no standard to use to address this. This has left develop teams to struggle with means to mitigate and address security risks when third party IP and associated components are integrated into today’s modern embedded systems.

Advice on how to compare inferencing alternatives and the characteristics of an optimal inferencing engine.

In the last six months, we’ve seen an influx of specialized processors and IP to handle neural inferencing in AI applications at the edge and in the data center. Customers have been racing to evaluate these neural inferencing options, only to find out that it’s extremely confusing and no one really knows how to measure them. Some vendors talk about TOPS and TOPS/Watt without specifying models, batch sizes or process/voltage/temperature conditions. Others use the ResNet-50 benchmark, which is a much simpler model than most people need so its value in evaluating inference options is questionable.

There are almost a dozen vendors promoting inferencing IP but none of them gives even a ResNet-50 benchmark.

The only information they state typically is TOPS (Tera-Operations/Second) and TOPS/Watt.

Let’s discuss why these two indicators of performance and power efficiency are almost useless by themselves.

Abstract - With increased number of mixed-signal SoC designs and accordingly mixed-signal verification needs, UVM as a proven verification methodology for complex digital SoC is imposed as a solution. However, many mixed-signal UVM verification approaches are present, with no standardized methods of connecting UVM environment with Mixed-Signal design. For these reasons, efficient Mixed-Signal design verification is becoming challenging and opens space for innovative verification solutions. This paper will show different ways to connect UVM environment with Mixed-Signal design when Verilog-AMS models are used.

Read the full blog here

High-performance SerDes represents critical enabling technology for advanced ASICs. This star IP block finds application in many networking and switching designs as well as other high-performance applications. So, when a new high-performance SerDes block hits the streets, it’s real news. eSilicon has been enjoying the spotlight on such an event. We recently announced silicon validation of our 7nm, 56G long-reach SerDes. We were happy to report in that announcement: “lab measurements confirm that the design is meeting or exceeding the target performance, power and functionality.” Anyone who has plugged a new and complex chip into a test fixture for the first time knows what this feels like.

click here to read the full blog

Page 1 of 18