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Escalating chip complexity and scale is an ever-present theme in any integrated circuit (IC) design discussion. The challenges are becoming especially acute as we move to the era of hyper-convergent ICs, which are not only larger and more complex, but also introduce new requirements to perform multi-dimensional verification of these highly integrated system-level chips.

Simply throwing more horsepower at the problem is no longer sufficient (although still needed). A more productivity-oriented workflow is essential to deal with the variety of verification challenges in a modern system-on-chip (SoC). Multiple verification methods need to work in concert, and overall productivity is just as important as individual tool performance. It calls for a revamped verification strategy. Call it a continuum. This post, originally published in the “From Silicon to Software” blog, shares what you need to know.

By Raja Tabet, Sr. VP of Engineering, and Anand Thiruvengadam, Product Marketing Director, Custom Design and Physical Verification Group

In our data-driven world, applications like high-performance computing (HPC) and artificial intelligence (AI) are taking center stage, delivering intelligence and insights that are transforming our lives. However, the growing complexities of HPC and AI designs are driving the need for much more complex semiconductor devices. Increasingly, multiple components and technologies are coming together in hyper-convergent designs to meet demands for bandwidth, performance, and power for these compute-intensive applications. To achieve power, performance, and area (PPA) targets, such complex chips need to be analyzed as a single system—an approach that’s difficult to support via traditionally disparate tools. In this post, originally published in the “From Silicon to Software” blog, we’ll examine the trend of IC hyperconvergence and explain why the traditional, disaggregated approach to circuit simulation is no longer sufficient.

As silicon chips grow larger and more complex, it becomes even more important to find and fix problems early in your design cycle—before the issues become more costly and challenging to resolve. After all, no one wants to deal with an SoC re-spin. Thanks to FPGA-based prototyping, pre-silicon software development and system validation have become integral parts of the design cycle.

A little more than two years ago, Synopsys became one of the inaugural partners of the IBM Research AI Hardware Center. As its name implies, the AI Hardware Center is a focused effort to address the challenge of developing a new generation of AI-enabled chips and systems. The Center is designed to be “… the nucleus of a new ecosystem of research and commercial partners collaborating with IBM researchers to further accelerate the development of AI-optimized hardware innovations.”

The goal of the initiative is straightforward: improve AI performance by 1,000x in 10 years.

In January, Mentor will become Siemens EDA and this is exciting news for our EDA customers. Siemens enables us to bring high levels of investment in research and development, to build new products, and to acquire best-in-class electronic design companies. Mentor has always pioneered digitalization of electronic design and Siemens brings world-class digitalization to big systems like planes, automobiles, factories, and cities. Connecting electronic design to big systems is the vision for our customers.

I’m not alone in viewing each and every early-stage startup as a beacon of opportunity. Some of the most innovative and world-changing ideas I’ve seen in recent years have come from those only just starting out on their journey.

However, the challenges early-stage startups face are no secret: they need to build investor confidence to secure funding, they need to innovate quickly and they need to do so while minimizing costs along the way.

For Arm it’s incredibly important that we help fledgling companies with the potential to do something great to get off the ground. So today, we’re launching a new zero-dollar program, Arm Flexible Access for Startups, to give early stage startups access to a broad range of our world-leading technologies, spanning processor designs, tools and support.

Meeting tapeout schedules and performance requirements are equally critical conditions for IC design success. Now engineers can do both, using innovative P2P resistance checking to find and debug ESD errors in their layouts.

מדינות שונות שפות שונות ובפרט בסין דיאלקטים שונים. למרות זאת יש מדינות בהן המהנדסים כותבים אנגלית אולם ברובן ההנדסה כתובה בשפה המקומית. אף על פי כן השפה השיווקית בחלקת מהמדינות היא אנגלית. ביפן, סין וטייוון מפרטים טכניים יכתבו ביפנית/מנדרין אולם בקוריאה הדרומית והודו באנגלית.

Before we get started here, I’ll assure you it’s not as it sounds. I’m not talking about the end of coverage as though it’s something we’ll stop using. The end in this case is the home stretch of any non-trivial ASIC or FPGA development effort – which is almost all of them nowadays – where coverage collection, analysis and reporting consumes a team on its way to RTL signoff.

There is probably not one embedded system that is not built without open source software, 3rd party silicon IP or manufactured far from the design and distribution centers that make and sell these systems. Those who want to secure the design and delivery chain have no standard to use to address this. This has left develop teams to struggle with means to mitigate and address security risks when third party IP and associated components are integrated into today’s modern embedded systems.

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