Applications for Embedded FPGA

Posted by 
in Blogs
23 September 2017

Market leaders in a wide range of markets are quickly embracing embedded FPGA technology because it significantly increases the return on investment required to bring complex chips to market. With readily-available, high-density blocks of programmable RTL in any size and with the features a customer needs, designers now have the powerful flexibility to customize a single chip for multiple markets and/or upgrade the chip while in the system to adjust to changing standards such as networking protocols. Customers can also easily update their chips with the latest deep learning algorithms and/or implement their own versions of protocols in data centers. In the past, the only way to accomplish these updates was through expensive and time-consuming new mask versions of the same chip.

FlexLogix Image 1 400 

Multiple Markets for Many Different Applications

Embedded FPGA arrays can be used anywhere chip designers need flexibility to address uncertainty and/or changing standards; or a range of market needs with high performance. Below are just a few of the markets where this technology is being applied:

  • Networking: programmable parsers, network protocols, security protocols and storage protocols
  • Data Center Acceleration
  • Wireless Base Station DFE (digital front end)
  • MCUs: reconfigurable I/O; I/O processing to offload the MPU; reconfigurable
  • accelerators
  • SoCs: I/O Mux; reconfigurable I/O; reconfigurable accelerators
  • SSD: programmable timing and ECC
  • Aerospace/Defense: integrated FPGA is smaller, lighter, lower power and can be implemented in rad-hard processes and/or trusted fabs

Need to Convert an FPGA to ASIC?
When evaluating embedded FPGA, many chip designers already have an FPGA design and they want to convert this to ASIC so they can reduce the cost. Using embedded FPGA enables them to keep some of the chip flexible so they can reconfigure and upgrade portions of the design that evolve and change over time. This is very important to chip designers because they never know what changes are looming in the near or distant future and they have to be quick to confirm and adapt.

FlexLogix Image 2 400

Reconfigurability is Key

Most companies today want reconfigurability – and data centers are a perfect example. Rather than a fork-lift upgrade when standards evolve, data centers want programmable chips so they can upgrade the data center’s ability during the life of the center without touching the hardware. This also gives the data center the option to customize for added competitive advantage. As Doug Burger of Microsoft said at a recent talk at FPL 2016, “ReConfigurable Clouds will change the world with the ability to reprogram a datacenter’s hardware protocols: networking, storage, security.” Embedded FPGA technology is the enabling technology that will allow this to happen.

Data centers are increasingly seeking out chips that can be programmed to evolve to
handle future versions of protocols and packets and that have accelerators to run certain tasks faster than x86 processors. As Microsoft and others have shown, FPGA can speed certain data center functions as compared to x86 processors since the bottleneck in performance is typically the PCI Express bus.

Implementing Embedded FPGA
An embedded FPGA can be provided either as soft IP or hard IP. Choosing to use hard IP provides an advantage because an FPGA is an array and not random logic. Thus, it lends itself to a much denser implementation (~4-6 times denser) if provided as a hard IP.

Hard IP also provides a validation opportunity. Because of the very high cost of chip designs today, chip designers will likely want to see the embedded FPGA IP proven in silicon before committing to integrate it into their SoC or MCU. If arrays are custom designed, each must be separately proven in silicon, which takes time and adds cost. But hard IP cores designed to operate standalone or be “tiled” or “arrayed” to build larger embedded FPGA arrays can eliminate the need for proving a custom design. IP that can be tiled enables the core to be implemented in silicon in, say, a 2x2 array, to prove out both the core and the core-to-core interconnect. Such proof also guarantees that any larger NxM array will work as well, freeing chip designers to implement such arrays with confidence – no further test required.

Embedded FPGA arrays can be integrated into an SoC or MCU in three common ways:

  • For an application in an MCU where different customers have different needs for specialized RTL blocks (logic to full coprocessor) running as a slave on the processor bus, the embedded FPGA can directly connect to the bus. Any kind of processor bus will work: APB, AHB, AXI. Below is a simple example of a direct connection to an APB bus with the logic in the embedded FPGA itself (the logic could also be hardwired outside of the embedded FPGA.)

    FlexLogix Image 3 400

  • For an application such as protocol processing, the array can sit in the control
  • and/or data path. In an application such as always-on processing in a battery-backed system, for instance, the embedded FPGA array can directly connect to and monitor/process data from a range of IOs.

    FlexLogix Image 4 400

  • And of course, a combination of the above functions is possible as well, such as an embedded FPGA block on a processor bus with direct IO connections.


Embedded FPGA is applicable to a wide range of markets and use cases. The first customer to announce that it was using this new technology was DARPA, the US Government's Defense Advanced Research Projects Agency. DARPA selected Flex Logix’s EFLX™ embedded FPGA and entered into an agreement for it to be made available to any company or government agency designing chips in TSMC 16FFC for use by any branch of the US Government. Other companies are also working on designs using embedded FPGA, but they don’t want to show their cards too early and tip off the competition.

Over time, embedded FPGA is expected to become so pervasive that it will be available on every significant foundry from 180nm to 7nm supporting a wide range of applications. The advantages in cost, performance, and power consumption are too great for chip designers to not take advantage of this innovative new development.

Last modified on Wednesday, 27 September 2017 05:27
Geoff Tate

CEO of Flex Logix, Inc.