The Case for Developing Custom Analog SoCs

Posted by  12 December 2012

Custom analog SOC (system-on-chip) designs are now a real option for many system houses and OEMs that previously found such designs outside their budgets. The reduction in fabrication costs for older-node processes (especially at 0.18µm and 0.13µm) and the availability of proven mixed-signal IP cores and subsystems, mean that an SOC solution can deliver significant savings on the BoM (Bill of Materials) making the previously unjustifiable expenditure on NRE (non-recurring engineering) costs now recoverable in very short time frames (of the order of a single year), even with relatively low-volume products.



Why use a custom analog SOC?

SOCs are ICs where all the components of an electronic system are integrated onto a single chip to meet a specific application need. A system may contain analog, digital, mixed-signal and often radio frequency functionality, integrated with an advanced processor and built-in memory blocks. Designing such systems on a single chip enables smaller, lighter, more-reliable and power-efficient systems to become a reality. More analog is now being moved into single SOCs presenting the challenge of integrating analog functionality in low geometries with complex digital functionality. But with architecture analysis and careful reuse of silicon-proven IP, i.e., "big A, small D" (big Analog, small Digital) SOC solutions are realizable and so, too, are many of the following advantages:

 

  • Lower unit costs - The cost of discrete components can become very expensive as performance demands increase. It makes sense to consider the potential savings that can be gained by replacing many discrete components with a single SOC incorporating RF & analog or mixed signal IP which can be customized for specific application requirements.
  • Differentiating features - Custom analog SOC designs allow designers to include unique features that may not have been available, or have previously fitted, with discrete components. This gives the product managers an opportunity to increase competitive differentiation of their products through the addition of higher performance functionality.
  • Security of design - Reverse engineering has long been an unwelcome element in the world of electronics. Using custom analog SOC designs makes reverse engineering significantly more difficult, more expensive and a much lengthier affair. This gives the advantage of having a differentiated product on the market for much longer before competitors have an opportunity to copy or compete.
  • Portability to different product lines - With the correct architectural analysis a single SOC design can meet the demands of different product design and manufacturing requirements. Designing a SOC solution that can be used in a range of different product lines provides the potential for cost reductions in future product developments.

The business case for custom analog SOC

Bringing these systems to production is now a real option for system houses and OEMs outside of the high volume consumer world for a variety of products including healthcare devices, industrial controllers and home appliances. Previously the balance between production costs and the NRE costs of a SOC design made this option unaffordable, but with the fabrication costs significantly reduced for designs at older process nodes, and the availability of proven IP that accelerates development schedules and lowers risk, that balance has now changed in favor of incurring those NRE costs even for low volume products.

An insatiable need for higher integration and lower unit cost forces high-volume consumer products (smartphones, tablets, etc.) to the most-advanced process nodes (28nm ramping in 2012) has freed up capacity in what are now mature process nodes (0.18µm and 0.13µm). In an effort to maintain fab utilization, manufacturers have lowered mask costs, in some cases, quite significantly.

In 2010 the GSA Wafer Pricing Survey (GSA, 2010) confirmed this and stated that the average mask-set pricing for 200-mm wafers manufactured at 0.35µm, 0.25µm, 0.18µm and 0.13µm had generally decreased year after year, with 0.18µm posting the largest decrease of 57% in Q3 2009 over Q3 2006. In Q3 2009, average mask-set pricing for 300-mm wafers manufactured at 90nm decreased 22% over Q3 2008. It is clear that an opportunity now exists for OEMs that traditionally could not justify analog SOC development NRE to do so targeting process nodes at 90nm and higher.

These more affordable fabrication costs, coupled with the cost-saving possibilities achievable through more-integrated designs afforded by SOCs, means that products can now be produced with large savings to the BoM. These large savings in BoM cost mean that even with relatively low-volume production, the NRE costs can be recovered early.

Using an NRE cost of $2 million as an example — a useful rule-of-thumb cost for a relatively complex SOC requiring approximately 12 months development time — where a BoM saving of $40 per unit is achieved, this NRE cost is recovered once volume sales exceed 50,000 units. Figure 1 illustrates this across different volume of sales and for different BoM savings per unit.

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Figure 1. Potential additional profit over product lifetime.

The following examples demonstrate how three products, previously achieved through discrete-component designs, were redesigned to custom analog SOCs. Each case brought its own set of technical challenges which were met through innovative use of available analog and mixed-signal IP and the experience of well-established engineering teams. The significant BoM reduction made the business case for each of these product managers.

Eliminating 400 components in a satellite-phone handset

The maker of a satellite-phone handset saw the opportunity to develop a much-smaller and more-convenient device – going from a back-pack sized unit to a candy-bar-sized unit. The goal was to architect the system into a two-chip solution. Work centered on the re-design of the radio transceiver from the RF through analog baseband and DSP while retaining compatibility with the existing satellite and ground infrastructure. Based on proprietary RF protocols and minimizing design risk, an advanced RF SOC platform was developed that not only exploits the latest proven silicon technology, but also incorporates the flexibility to facilitate future product developments. This required an ability to look at the whole system and understand the design space and critical constraints.

The resulting RF SOC platform removed the requirement for expensive external components including IQ demodulators, IF transceivers, 14-bit ADC and DAC, linear regulators, temperature sensors and auxiliary circuits. This reduced the PCB complexity and size, and simplified the product design. On the baseband-processing side, a much-more efficient and simplified processor and DSP solution was employed and customized to the application, removing the need to use standard ASSP parts, which were overly complex and provided processing power far in excess of what was required for the application.

In all, over 400 components were removed from the BoM, and the solution consisted of:

  • A digital baseband-processing SOC replaced 200 discrete components with an estimated saving of $30 per unit.
  • An innovative customized RF and analog IC replaced 200 components at an estimated saving of $33 per unit.


This redesign saw, in addition to a much-improved feature set and lower power requirements in the new product, a reduction in BoM and design complexity which made the NRE costs recoverable in the second year of projected sales.

The benefits of working with a strategic design partner

The example of a satellite phone modem highlights the advantage of working with long-term strategic design partners, capable of developing a roadmap of product improvements. The same satellite phone handset maker realized further system-cost efficiency through a redesign of the power-management/ power-amplifier system which permitted the use of lower-cost external power amplifiers.

A proven design methodology using a combination of a top-down and bottom-up design allows for efficient system partitioning while enabling optimization of performance at the transistor level. Use of proven design and review processes based on Verilog AMS modelling, facilitates the bottom-up and top-down to merge effectively and ensures adequate verification of the design prior to tape-out.

The RF and analog IC incorporates an LNA (low-noise amplifier), power amplifier drivers and RF mixers. This combined RF and analog IC, with the new power amplifier cost options achieved at an estimated unit cost saving of $30, made the NRE costs recoverable in the second year of projected sales. In addition, the reduction in the BoM reduced design complexity and simplified the supply chain, enabling further cost savings.

Hitting a particular market price-point was the major challenge for this maker of a wireless communication device. The company was able to realize its objective with a single-chip RF CMOS IC. The elimination of over 610 components resulted in an estimated per unit saving of $77.

Integrating high switching frequency DSP cores and other digital functions with sensitive RF blocks such as SAW filters, LNAs and mixers and high-performance PLLs on the same substrate was the technical challenge as a balance needed to be struck between maintaining high performance and noise isolation to ensure robust functional performance. Leveraging silicon-proven subsystem IP which was optimized for power, performance and robustness, ensured that risk was significantly reduced and development time shortened, in turn reducing the development NRE.

Even with the modest product volume expected, the significant savings in BoM enable this wireless-communication device maker see a return on investment in the second year.

How best to achieve

The complexity of SOC designs means that partnering with a proven SOC-design house lowers risk and provides a faster time-to-market. The ideal partner has experience in innovative SOC design, understands the system components and various CMOS process options, and knows which available analog and mixed-signal IP will benefit the implementation.

S3 Group, for example, brings 25 years of such experience, engineering expertise and strong relationships with semiconductor foundries and fabless ASIC suppliers. As well as having a comprehensive portfolio of silicon-proven RF and mixed-signal IP, S3 Group uses its platform and subsystem-development knowledge to help partners find solutions that enhance their product development roadmaps. SOC solutions must be designed for manufacturing and verified to the highest level, and S3 group has the experience to look at the whole system and to understand the critical constraints.

In summary

System houses and OEMs can now realize their products in custom analog SOCs in a timely and affordable way. The shift in fabrication costs for mature process nodes has made analog SOC designs a real option when balanced against potential savings in BoM per unit, and the NRE costs are shown to be recoverable very early, even at low product volumes. Innovative SOC solutions are a challenge, but one where additional features can be realized in smaller, lighter, more-reliable systems with greater security.

Partnering with a design house with a clear understanding of all the system components and of the various technology options for implementation helps realize the silicon development in a cost-effective and low-risk manner.

Last modified on Wednesday, 09 January 2013 15:38