Breakthrough Interconnect Makes EFPGA Dense And Portable

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04 April 2018

In the 30 years since FPGAs were first developed, they have become bigger and faster, but their basic architecture has remained unchanged. One FPGA company executive once said they don’t really sell programmable logic, they sell programmable interconnect, because 70-80% of the fabric of an FPGA is the traditional mesh fabric which routes the signals programmably between all of the logic blocks. And as the FPGA gets bigger, the amount of interconnection typically needs to grow to avoid routing problems (complexity scales with N2).

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Flex Logix was founded because the co-founder Cheng Wang came up with a way to make a better FPGA through the use of a novel new interconnect that could cut the FPGA fabric size almost in half, while leaving all other things equal such as process choice and choice of full-custom/standard-cell. This Interconnect technology is called XFLX.

XFLX was so great that when Cheng and others wrote a paper on it, they won the Outstanding Paper award at ISSCC 2015. This award is typically won by giant companies such as Intel and Bosch. The fact that it was won by a few University PhDs was just the

first indication that Cheng and his peers had developed something truly revolutionary in the world of chip design.

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About the XFLX Interconnect

Not only does this new XFLX interconnect cut area, but it also reduces the number of metal layers needed. This turns out to be very valuable because there are often dozens of metal stacks in a given process node/variation. By using only 5, 6, 7 metal layers, it means that the eFPGA IP is compatible with almost all metal stacks. In contrast, solutions that use a large number of metal layers, such as FPGA chip companies, require customers to adopt their metal stack OR re-route designs, taking time and doing surgery on the GDS.

What is XFLX? It is a Boundary-Less Radix Interconnect Network. At first glance, it appears to be a hierarchical network, which has been tried before, but it incorporates numerous improvements to improve spatial locality so as to cut area while at the same time maintaining performance.

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As it scales, the complexity grows, but as a rough function of N*logN, which is much less than the rate of complexity increase for the traditional mesh.

When Cheng and others won the ISSCC Prize, technical executives from around the industry took notice. Because XFLX was so different from what they used in the past, they first thought they would have to re-do all their place-and-route software, which had been invested in heavily for more than a decade. There was also skepticism whether it would really perform as advertised in production quality silicon. Neither of these concerns proved to be true.

 

Fast Forward to Today

Since those initial meetings, the XFLX interconnect has been implemented on TSMC 40, 28 and 16nm. It has been improved in a “Gen 2” architecture on 16 and will soon be on 28nm. This technology has also been patented, with two patents issued to Flex Logix that name Cheng Wang as the inventor.

To test XFLX and do a density comparison, Flex Logix used data from a competitor who licenses eFPGA IP based on their FPGA chips. The results showed that the Flex Logix platform was within 5-10% of their density in terms of LUT4-equivalents/mm2, even though they used a full-custom design whereas Flex Logix used standard cells. The superior density of XFLX allowed it to match their density AND enable superior portability.

By using fewer layers of metal, the Flex Logix platform is compatible with most memory stacks. Since it uses standard cells, it can support multiple process variations within a node with one GDS (for example, 16FF+/16FFC/12FFC or 28HPC/HPC+) whereas eFPGA IP based on an FPGA chip has to be re-routed (if possible) for each metal stack and has to change their GDS to redesign full-custom circuitry to move process variations where we can use the same GDS.

The Future

Traditional interconnect technology is not capable of achieving the silicon-proven scalability the industry needs. Customers not only want proven eFPGA IP in silicon, but they also want it in very different sizes. Using the XFLX interconnect, eFPGA has the scalability to deliver a few thousand LUTs, a couple hundred thousand LUTs, or any size in between. This will be a major competitive advantage when designing MCUs and SoCs in the future

Last modified on Wednesday, 04 April 2018 11:09
Geoff Tate

CEO of Flex Logix, Inc.