PDN (Power Delivery Network) Verification Coverage

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in Blogs
26 December 2013

Abstract

Power grid verification is considered as a challenge since no industry standard that if the design team is following will result in a proof power grid for power and signal integrity issues, in other areas there is a verification plan with many checks need to be performed and when all are done successfully the design is considered verified and can continue to TapeOut.

Having a high coverage in power grid power and signal integrity means that the design after TapeOut is not exposed to a logic failure due to a critical timing path that was violated, or an analog design that became not functional because it got a noise level which is way beyond it's specifications, another failure aspect is a jitter violation which can cause a logic failure, but before that is can cause a violation of jitter target on the DDR chip clock pin.
In this paper a verification flow to get a high power grid verification coverage will be presented, while keeping low effort and catching the design weak point early in the design cycle.


Power and signal integrity verification flow

The power grid verification coverage flow comprises of 8 stages, each stage is increasing the verification coverage, it is recommended to execute all stages and in the correct order, following is a description of every stage and its contribution to the total coverage.

Early design stage

In early stages of the design it is recommended to use an early power grid prototyping combined with early RTL level power estimation, having a power grid prototype that meets the design requirement can save major design changes later in the design cycle

Design inputs check stage

Second stage is to verify the design inputs, if part are not complete there will be a risk that the missing data that was not included when running the design power and signal integrity could change the simulation results.
During this stage, all input design data is verified, missing information is reported with its count in the design, this measure can be used to prioritized the completion of the missing data.
On top of design inputs, the design simulation setting is also checked and the designer is getting a report for required fixes, some examples are: missing devices in libraries, required Frequency for getting a good capture of the design power

Design weaknesses check stage

Design weaknesses check is done after reading the design in and running extraction, many issues can be resolved in this stage including finding missing vias, detecting shorts, detecting un-connected wires and instances.
Special test in this stage is checking the quality of the power grid, while LVS is checking the existence of connectivity, We need to check the connection quality, the power grid resistance to every device will be reported, high resistance will decrease noise immunity and can point to IR drop issues and EM in static and dynamic simulations, solving high resistance connection to a device in this stage will save a lot of un-necessary debug time during next stages.

Static simulation check stage

Static simulation stage is the first recommended simulation it is essential to find
average issues but it is not capable of capturing the dynamic effects like:

  • Package inductance effect
  • Decaps effect
  • Simultaneous switching effect

During this stage and due to the average nature of the simulation, coverage is increased mainly due to the following items:

1. Check that the design metal density is adequate to drive the design average power consumption.
2. Check that the number of pads can drive the design average current with respect to the pads maximum current specifications.
3. If It's a low power design using power gates, check that the number of power gates can drive the design average current to the switched units without any major IR drop.

Dynamic simulation: Guided vectorless check stage
When moving from static simulation to dynamic it's highly important to include the package data, high inductance in the package can increase the dynamic IR drop significantly.
First recommended dynamic simulation is the Vectorless one, even it is not including an accurate design switching information, using a built in engine in flow to detect design weak points, considering each instance: Function, toggle, timing overlap, power, frequency and weakly connection to the power grid.
Vectorless simulation is highly important for the verification coverage as it's able to find the design weak points.

Guided Vectorless

Guided Vectorless is when the designer is adding design related activity and power information to make the simulation more realistic.
Dynamic simulation: Scan check stage
Scan test is reflecting the biggest current peak consume by the design in a dynamic simulation, in this case all FF's are getting the same clock frequency and the logic connectivity is done using SCAN interfaces SI and SO,
the simulation can be done in Vectorless mode when ATPG information about SCAN order is inserted to simulation

Dynamic simulation: RTL VCD stage

RTL VCD is not always available during TapeOut time, using it can get a more realistic switching scenario,
but is limited to a specific vectors that are not covering the complete design, in this case a state propagation can be used
and the resulted power calculation will be more accurate, switching time is still taken from static timing data and can reflect a worst case
than actual toggle time, the benefit in RTL VCD compare to GL VCD is the size of the VCD files,
small size is obtain since it's based on simulators internal state propagation engine to generate the toggle data for the combinational cells.

Dynamic simulation: GL true timing VCD check stage

GL true timing VCD includes the propagated delay information in the simulation,
having both accurate information of every instance toggle and switching time,
this simulation is very accurate and combined with high accuracy APL's and package info and fine time step,
the simulation results can compared to silicon.

Conclusions
Power grid verification target is to have a high design failure coverage,
early detection of design faults and weaknesses,
early prototyping and grid planning, failure root cause analysis to improve productivity,
full integration of Board, Package and Die effects