Analysis of the Winbond W971FF6JB-25 1 Gb SDRAM using Buried Wordline Technology

Posted by  23 June 2010

Metal gates are back. First Intel used them in its microprocessors and now Winbond in its latest DRAM.

To the broader market, the move to metal gates is understood as being based on pure electrical performance (i.e., speed), but in the case of the DRAM device, this new technology also suggests a significantly lower manufacturing cost. By way of a history lesson, metal gates haven’t been used in production for several decades because the lack of self-aligned source/drains added unnecessary process complexity. Ironically, in this product, they actually simplify the process.

This DRAM technology is called “Buried Wordline” (bWL) and is licensed from the now defunct Qimonda. The Winbond 1 Gb SDRAM features a 0.025 µm2 cell in a 6F2 layout. Sinking the wordline below the substrate surface eliminates stray capacitance between the wordline and contacts, and reduces the bitline/wordline capacitance, ultimately lowering power consumption.

All of the other major DRAM manufacturers, including Elpida, Hynix, Micron, and Samsung, have maintained generally the same overall process design from DDR to DDR 3 SDRAMs, as the devices were scaled from 90 nm to 40 nm to achieve higher capacity SDRAM memory. All of these major DRAM manufacturers use some flavor of recessed channel array transistor (RCAT) wordline transistors, with a relatively complex sidewall spacer structure, a separate metal level for bitline, and multi-level poly plugs to contact capacitor cells to wordline transistor source/drain (S/D), which are in many instances offset from each other and from the capacitor cells. Further, most of the SDRAMs use double-sided capacitor tubes for their DDR 3 SDRAMs, supported by an extra dielectric layer near the top plate for mechanical stability.

Winbond’s SDRAM process design, at least at the 65 nm node, is significantly simpler. By burying the metal gate wordline, there is no need for a complex sidewall structure and separate metal level for the bitline. The silicided poly layer that is used for transistor gates in the peripheral circuitry is also used for bitlines in the memory array. This reduces the number of poly plug levels used to contact the capacitor cells to the wordline transistor S/D to just a single level, and reduces the associated complexity of plug alignment and plug-to-plug resistance due to carefully designed plug-to-plug offsets. The process complexity is further reduced by using dummy wordlines instead of STI to isolate active wordlines (which may make it harder to scale down to 40 nm and below due to increased cross talk).

The simplified process can be observed in both cross section and planar view of the capacitor. Interestingly, in the lower part of the stack, ZAZ (zirconia/alumina/zirconia) high-k dielectric is only used on the inside of the TiN cylinder, while the upper section uses ZAZ on both the inner and outer surfaces. This structure gives a lower overall cell capacitance compared with the full double-sided structure, but presumably it is still sufficient to give a sense-able signal to the bitline. However, the simplified process should give an excellent cost and yield advantage; this design may well make a very competitive part for Winbond for all but the most densely populated boards. And with devices like the iPad seemingly having tons of extra room for electronics – cost may well be the deciding factor for a lot of electronics.

Capacitor stack in the Winbond 65 nm 1 Gb SDRAM

Plan view sections of the Winbond 65 nm 1 Gb SDRAM capacitors, showing the upper (bottom image) and lower sections

Last modified on Wednesday, 23 June 2010 21:17