ESD Robustness Verification for System-on-a-Chip Designs

Posted by  05 July 2010

Given the complexity of present day’s System-on-chip (SoC) designs, higher resistance of the power and ground meshes, increased device density, and the greater sensitivity of the metal structures to breakdown in the sub micron technology nodes, the proper design and placement of ESD protection circuitry has become quite critical.

Most engineering teams use well-defined rules for placement; however advanced verification technologies aimed at checking the proper placement and connectivity of the protection circuitry are either not available or if available are rarely used. Visual inspection, plot checking or design rule based checks are usually employed but these methods do not provide sufficient verification coverage needed to ensure that (a) proper connectivity is maintained, (b) the overall resistance of the discharge paths is below threshold  limits, and (c) the wires are not subjected to break-down from the discharge current.

The required solution for verifying the full-chip level, placement and connectivity of ESD protection circuitry for various discharge mechanisms is described in Figure 1. Special care need to be given to the capacity requirement of a full chip power delivery network simulation and run time is also a major factor. When simulation results are received, a design results exploration with a fix and optimize capability is used to ensure a fast design improvement round.

Figure 1 outlines the analysis flow. One input data is the layout of the SoC (usually in the form of a DEF/GDSII file) which provides all the power and ground geometries (wires and vias) that connect the ESD circuits to the pads. The layout also contains the placement information for the standard cells, memories, pads, analog blocks and the diodes. Other inputs include the ESD rules that define the maximum allowed resistance between various structures like a pad to a clamp cell or from one clamp cell to another or from one pad to another pad, Simulation results are compared against the imported set of rules and reporting if the rules are met successfully. ESD designers want to ensure that all the pads in the chip that are connected to the clamp cells meet associated design rules (for HBM and MM discharge events) and that all the transistors in the circuit had proper connectivity to the clamp circuits(for CDM discharge events). Additionally the tool need to verify that the wires and vias can handle high current flow during a discharge event by comparing the current density against established limits. Farther requirement is the IP level validation through time-domain simulation of a discharge event. In this simulation, using a Spice-like engine, the target is to analyze the circuit consisting of the clamp cells where a special model using snap-back I-V profile is required, the PMOS/NMOS devices and substrate/power-ground/package parasitics and predict the discharge process providing guidance on areas where device/wire failure can happen.

Last modified on Wednesday, 07 July 2010 18:42