SemIsrael Verification Day 2011
Welcome to SemIsrael Verification Day
The Largest and Most Focused Event for the Silicon Verification Sector!
Read The Full Event Agenda
Venue: Green House, Tel Aviv (map); Free Parking Space is Available
Date: March 2nd, 2011
Time: 8:15AM - 15:30PM
- A First of its Kind in Israel - Largest and Most Focused Event for the Silicon Verification Sector!
- Uniquely tailored for Verification Professionals and Executives
Why should you attend the SemIsrael Verification Day:
- Come and meet the Who's Who in the Verification space
- Get the most updated current technology and know-how from leading vendors
- Best networking event
- Enjoy the unique ambience and quality of SemIsrael professional events
Agenda:
8:15-9:10 | Refreshments, Registration & Expo | |
9:10-9:15 | Welcome | by Shuka Zernovizky, SemIsrael |
9:15-9:40 | Solving Verification Challenges Presented by Multiple Clock Domains | by Eugene Mandel ,Verification Specialist, Mentor Graphics |
9:40-10:05 | Highlights From DV Club 2010 Presentations | by Eric T. Hennenhoefer, President & CEO and Co-Founder, Obsidian Software Inc. |
10:05-10:30 | UVM 1.0 Update | by Jacob David, Applications Consultant, Synopsys |
10:30-10:55 | Advanced Verification Combined With LAB Testing - Knowhow and Benchmark | by Hagai Arbel, CEO, Veriest Venture |
10:55-11:20 | The Spectrum of Applications for Formal Verification | by Ziyad Hanna, Jasper Vice President of Research, Chief Architect, and General Manager of Jasper Israel, Ltd. |
11:20-11:45 | Next Generation Verification IPs | by Deepak Kumar, Senior Design Engineer at nSys Design Systems |
11:45-12:15 | Coffee, Snacks & Visit to the Expo | |
12:15-12:40 | Learning Microarchitectural Behaviors To Improve Stimuli Generation Quality | by Michal Rimon , Research Staff Member, IBM Haifa Research Lab |
12:40-13:05 | What Do You Need to Know to Achieve CDC Signoff | by Yoav Arnon, VP Technical Services, Satris Group Ltd, Real Intent |
13:05-13:30 | High Speed ASIC Emulation | by Miguel Koch, VP Sales, EMEA, EVE |
13:30-13:55 | Simulations acceleration of a large design using RocketSim | by Eitan Zehavi, Senior Director of Engineering at Mellanox |
13:55-14:20 | Functional Qualification of Verification Environments for Digital Logic Designs | by Paul Nottingham, European Director, Springsoft |
14:20-15:00 | Lunch |
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15:00-15:30 | Desert, Lucky Draw, Visit to the Expo |
Please fill in your personal details to guarantee your participation
Participation is free - and early registration is required.